1. Field of the Invention
The present invention relates to a ferroelectric memory, and more particularly, to a ferroelectric memory in which a memory cell comprises ferroelectric capacitor elements to store memory formed on a semiconductor substrate and a switching transistor and a method of preparation for writing therein.
2. Description of the Related Arts
In a conventional ferroelectric memory, there has been employed a method of data storage utilizing two ferroelectric capacitors connected in series, as shown, for example, in Japanese Patent Application Laid-Open No. 66897/89.
FIG. 1 is a diagram showing an arrangement of the ferroelectric memory utilizing two ferroelectric capacitors connected in series as shown in Japanese Patent Application Laid-Open No. 66897/89. Each of memory elements 120, 122, 124 and 126 is a memory element utilizing two ferroelectric capacitors connected to a memory cell transistor in series. A first word line 130 is coupled to gate electrodes of transistors within memory elements 120 and 122. A second word line 132 is coupled to gate electrodes of transistors within memory elements 124 and 126. A first bit line 134 and a second bit line 136 intersect the word lines 130 and 132 at right angles. A first pair of common lines 138 and 140 is capacity-coupled to each drain electrode of two ferroelectric capacitors within memory elements 120 and 122. A second pair of common lines 142 and 144 is capacity-coupled to each drain electrode of two ferroelectric capacitors within memory elements 124 and 126.
FIG. 2 is a timing diagram of the memory arrangement shown in FIG. 1. A method of reading data which are stored in memory elements 120 and 122 and writing new data to the memory after the reading out will be described hereinafter.
At time T.sub.0, each of bit lines 134 and 136 is charged to 2.5 V preliminary. By raising electric potential of the common line 138 to 5 V at time T.sub.1 and, subsequently, electric potential of word line 130 to 5 V at time T.sub.2, each of electric potentials of bit lines 134 and 136 either goes up or down immediately after T.sub.2 at time T.sub.3, depending upon whether data are stored in memory elements 120 and 122. Signals generated on the bit lines 134 and 136 are then bound to be at either 5 V or 0 V at time T.sub.4, by sense amplifiers 146 and 148 which are coupled to the bit lines 134 and 136, respectively, and operate in differential mode.
Then, in order to write new data on memory elements 120 and 122 at time T.sub.5, electric potential of word line 130 is raised to 7 V and electric potential of common line 138 is dropped to 0 V. Next, electric potentials of common lines 138 and 140 are changed to 5 V at time T.sub.6 and electric potentials of common lines 138 and 140 are changed to 0 V at time T.sub.7. Further, electric potential of word line 130 is set to 0 V at time T.sub.8 and electric potentials of bit lines 134 and 136 are recharged to 2.5 V at time T.sub.9. Now, it is ready to respond for the next writing.
However, the related arts described above have the following problem. That is to say, because of independent setting of common lines 138 and 140, when both of their electric potentials are changed at time T.sub.6 or T.sub.7, the timing of these changes can be slightly off, which brings about a difference between electric potentials of the common lines 138 and 140, reverses the polarization of ferroelectric capacitors and thereby results a deflection in writing data.